The XRF4 System Controller is built on the AMD Kria™ K26 SOM. This SOM is a compact embedded system platform that integrates a custom-built AMD Zynq™ UltraScale+™ MPSoC with double-data rate (DDR) memory, nonvolatile storage device, security module, and aluminum thermal head spreader. This SOM plugs into the XRF4 RF baseboard.
The SOM provides a combination of fixed and user-defined functional interfaces, enabling the user to expand various control interfaces, such as the I2C, SPI, bi-directional GPIO, etc. For detailed information and specifications, see the Kria SOM website.
For the XRF4 system, a standalone Linux operating system is running on the SOM application processing unit (APU). The applications running on the SOM control the XRF4 system booting and the behavior of the baseboard and each slice card. Simultaneously, the SOM can be served as a peripheral subsystem of the AMD DFE system. The DFE system running on the ZCU670/ZCU208 board and its GUI controller can issue commands to the SOM APU for real-time control of the XRF4 baseboard or RF slices.
The following figure shows the general architecture and interface of the XRF4 system controller.
The 32 GPIOs (ADCIO and DACIO) connect the ZCU board and SOM through the XRF4-RFBB. These GPIOs are used for TDD timing control signals, frame sync, and SPI.
The SOM controls XRF4 slices through the SPI, I2C, and GPIOs. These interfaces provide the flexibility to implement power monitoring, gain control, temperature monitoring, and channel selection. Additionally, an EEPROM is included on each RF slice to store key slice configurations.
The physical SPI and I2C connections are shared by all slices through onboard demultiplexing. Only one slice can be selected at a time. Consequently, it is not recommended to use SPI and I2C as real-time control signals.
Conversely, the slice GPIOs are generated in the programming logic (PL) domain of the SOM FPGA. Consequently, these signals can implement real-time control. Each slice supports up to eight GPIOs (including the two designated TDD timing signals). These GPIOs can also be controlled by the SOM processing system (PS) subsystem.