Transceivers - UG1612

VEK280 Evaluation Board User Guide (UG1612)

Document ID

UG1612

Release Date

2024-01-31

Revision

1.1 English

The Versal device has 32 PL GTYP transceivers. The following table contains the mapping to hardened features, quads, channel locations, as well as general features.

Table 1. Transceiver Mapping
		XCVE2802
FMC+	FMCP1_DP4	CH0	GTYP Quad 206 X1Y4 CC [L]	PCIe X1Y2	PCIe X0Y2	GTYP Quad 106 X0Y4 BE [RN] (RCAL)	CH0	Versal_HSDP	HSDP/ SFP28
	FMCP1_DP5	CH1					CH1	HSDP_VERSAL_SYSCTL
	FMCP1_DP6	CH2					CH2	[UNUSED]
	FMCP1_DP7	CH3					CH3	SFP28
	RC21008A_GTCLK1_OUT7	REF0					REF0	HSDP_156_25_REFCLK
	FMCP1_GBTCLK1_M2C	REF1					REF1	RC21008A_GTCLK1_OUT8
	FMCP1_DP0	CH0	GTYP Quad 205 X1Y3 CB [L] (RCAL)	PCIe X1Y1	CPM5	GTYP (CPM5) Quad 105 X0Y3 BD [RS] (RCAL)	CH0	PCIe Lane3	PCIe Gen4x16
	FMCP1_DP1	CH1					CH1	PCIe Lane2
	FMCP1_DP2	CH2					CH2	PCIe Lane1
	FMCP1_DP3	CH3					CH3	PCIe Lane0
	RC21008A_GTCLK1_OUT6	REF0					REF0	PCIe_CLK0
	FMCP1_GBTCLK0_M2C	REF1					REF1	[UNUSED]
HDMI 2.1	HDMI_CH0	CH0	GTYP Quad 204 X1Y2 CA [L]	MRMAC X0Y1		GTYP (CPM5) Quad 104 X0Y2 BC [RS]	CH0	PCIe Lane7
	HDMI_CH1	CH1					CH1	PCIe Lane6
	HDMI_CH2	CH2					CH2	PCIe Lane5
	HDMI_TX_CLK_C / HDMI_RX_CLK_C	CH3					CH3	PCIe Lane4
	HDMI_RCLK_OUT_C	REF0					REF0	PCIe_CLK1
	HDMI_8T49N241_OUT_C	REF1					REF1	[UNUSED]
			VDU	PCIe X1Y0		GTYP (CPM5) Quad 103 X0Y1 BB [RS]	CH0	PCIe Lane11
							CH1	PCIe Lane10
							CH2	PCIe Lane9
							CH3	PCIe Lane8
							REF0	PCIe_CLK2
							REF1	[UNUSED]
			VDU	MRMAC X0Y0		GTYP (CPM5) Quad 102 X0Y0 BA [RS]	CH0	PCIe Lane15
							CH1	PCIe Lane14
							CH2	PCIe Lane13
							CH3	PCIe Lane12
							REF0	PCIe_CLK3
							REF1	[UNUSED]
			VDU	HDIO Bank 401 AA	PMCDIO Bank 503	LPDMIO Bank 502
			VDU	HDIO Bank 400 AB	PMCMIO Bank 501	PMCMIO/PMCDIO Bank 500