[Figure 1, callout 2]
POR_B is the Versal device processor reset, which can be controlled by:
- SYSCTLR (U125)
- PC4 header (J36)
- FTDI USB JTAG chip (U20)
The VEK280 board POR circuit is shown in the following figure. U235 allows directional open drain level shifting for all of these masters, and J326 allows them to be bused together if desired. The TPS389001 U10 supervisor chip holds POR_B off until power is valid.
Figure 1. POR_B Reset Circuit
