PMC and LPD MIO

VEK280 Evaluation Board User Guide (UG1612)

Document ID
UG1612
Release Date
2024-01-31
Revision
1.1 English

The following sections provide the MIO peripheral mapping implemented on the VEK280 evaluation board. See the Versal Adaptive SoC Technical Reference Manual (AM011) for more information on MIO peripheral mapping. Additional signal connectivity can be located in the following schematic sections:

  • Bank 500: See schematic page 10
  • Bank 501: See schematic page 10
  • Bank 502: See schematic page 11

The following table provides MIO peripheral mapping implemented on the VEK280 evaluation board. The Versal device bank 500, 501, and 502 mappings are listed in the following table.

Table 1. MIO Peripheral Mapping
Bank MIO # Device Signal I/O Notes
500 0 OSPI PMC_MIO0_OSPI_CLK O
1 PMC_MIO1_OSPI_DQ0 I/O
2 PMC_MIO2_OSPI_DQ1 I/O
3 PMC_MIO3_OSPI_DQ2 I/O
4 PMC_MIO4_OSPI_DQ3 I/O
5 PMC_MIO5_OSPI_DQ4 I/O
6 PMC_MIO6_OSPI_DQS I/O  
7 PMC_MIO7_OSPI_DQ5 I/O
8 PMC_MIO8_OSPI_DQ6 I/O
9 PMC_MIO9_OSPI_DQ7 I/O
10 PMC_MIO10_OSPI0_CS_B O
11 Regulator Enable GPIO PMC_MIO11_VCC_AUX_1V2_EN O See Table 1
12 OSPI PMC_MIO12_OSPI_RST_B O
13 USB PMC_MIO13_USB_RST_B O  
14 PMC_MIO14_USB_DAT0 I/O  
15 PMC_MIO15_USB_DAT1 I/O  
16 PMC_MIO16_USB_DAT2 I/O  
17 PMC_MIO17_USB_DAT3 I/O  
18 PMC_MIO18_USB_CLKOUT O  
19 PMC_MIO19_USB_DAT4 I/O  
20 PMC_MIO20_USB_DAT5 I/O  
21 PMC_MIO21_USB_DAT6 I/O  
22 PMC_MIO22_USB_DAT7 I/O  
23 PMC_MIO23_USB_DIR I/O  
24 PMC_MIO24_USB_STP O  
25 PMC_MIO25_USB_NXT I/O  
501 26 SD PMC_MIO26_SD_CLK O  
27 PMC_MIO27_SD_DIR1 O  
28 PMC_MIO28_SD_DET I  
29 PMC_MIO29_SD_CMD I/O  
30 PMC_MIO30_SD_DAT0 I/O  
31 PMC_MIO31_SD_DAT1 I/O  
32 PMC_MIO32_SD_DAT2 I/O  
33 PMC_MIO33_SD_DAT3 I/O  
34 PMC_MIO34_SD_SEL I/O  
35 PMC_MIO35_SD_DIR_CMD O  
36 PMC_MIO36_SD_DIR0 O  
37

Factory/CANFD0

See CAN Interface

PMC_MIO37_COMBINED I/O Selectable J406, Factory/CANFD0_INH_B
38

CANFD0

See CAN Interface

PMC_MIO38_CAN0_nSTB O Standby mode control input
39 SYSMON I2C PMC_MIO39_SYSMON_I2C_SCL O  
40 PMC_MIO40_SYSMON_I2C_SDA I/O  
41 PMC_MIO41_SYSMON_I2C_ALERT I/O  
42 UART PMC_MIO42_501_RX_IN I  
43 PMC_MIO43_501_TX_OUT O  
44 I2C1 PMC_MIO44_501_LP_I2C1_SCL O  
45 PMC_MIO45_501_LP_I2C1_SDA O  
46 I2C0 PMC_MIO46_501_I2C0_SCL I/O  
47 PMC_MIO47_501_I2C0_SDA I/O  
48 GEM0 PMC_MIO48_GEM_RST_B O  
49 Regulator Enable GPIO PMC_MIO49_VCC_PSLP_EN O See Table 1
50 PCIe PMC_MIO50_PCIE_WAKE_B O  
51 SD PMC_MIO51_SD_BUSPWR O  
502 0 GEM0 LPD_MIO0_GEM_TX_CLK O  
1 LPD_MIO1_GEM_TX_D0 I/O  
2 LPD_MIO2_GEM_TX_D1 I/O  
3 LPD_MIO3_GEM_TX_D2 I/O  
4 LPD_MIO4_GEM_TX_D3 I/O  
5 LPD_MIO5_GEM_TX_CTL I/O  
6 LPD_MIO6_GEM_RX_CLK I  
7 LPD_MIO7_GEM_RX_D0 I/O  
8 LPD_MIO8_GEM_RX_D1 I/O  
9 LPD_MIO9_GEM_RX_D2 I/O  
10 LPD_MIO10_GEM_RX_D3 I/O  
11 LPD_MIO11_GEM_RX_CTL I/O  
12 Regulator Enable GPIO LPD_MIO12_VCC_PSFP_EN O See Table 1
13 Regulator Enable GPIO LPD_MIO13_VCC_SOC_EN O See Table 1
14

CANFD0

See CAN Interface

LPD_MIO14_CANFD0_RX I
15 LPD_MIO15_CANFD0_TX O  
16

CANFD1

See CAN Interface

LPD_MIO16_CANFD1_TX O  
17 LPD_MIO17_CANFD1_RX I
18 PCIe PCIE_PERST_B I  
19 PCIE_PERST_B I  
20 Regulator Enable GPIO LPD_MIO20_VCC_PL_EN O See Table 1
21 Fan MIO21_FAN_PWM_VERSAL O Versal device fan PWM
22 MIO22_FAN_TACH_VERSAL I Versal device fan tach
23 Regulator Enable GPIO LPD_MIO23_VADJ_FMC_EN O VADJ_FMC enable
24 MDIO LPD_MIO24_GEM_MDC O GEM MD clock
25 LPD_MIO25_GEM_MDIO I/O GEM MD I/O