[Figure 1, callout 12]
Bus I2C1 connects the XCVE2802 U1 PS bank 501 and the XCZU4EG system controller U125 PS bank 501.
The detailed device connections for the feature described in this section are documented in the VEK280 evaluation board XDC file, referenced in Xilinx Design Constraints.
Figure 1. I2C1 Bus Topology
U34 is an I2C addressable 128-Kbit serial I2C bus EEPROM. It has two
addresses associated with it. Address 0x54 is used
when the memory array is accessed. When using 0x5C, the identification page is accessed.