Overview

VEK280 Evaluation Board User Guide (UG1612)

Document ID
UG1612
Release Date
2024-01-31
Revision
1.1 English

The Xilinx design constraints (XDC) file template for the VEK280 board provides for designs targeting the VEK280 evaluation board. Net names in the constraints listed correlate with net names on the latest VEK280 evaluation board schematic. Identify the appropriate pins and replace the net names with net names in the user RTL.

See the Vivado Design Suite User Guide: Using Constraints (UG903) for more information.

The HSPC FMCP connector J51 is connected to the AMD Versalâ„¢ device U1 banks powered by the variable voltage VADJ_FMC. Because different FMC cards implement different circuitry, the FMC bank I/O standards must be uniquely defined by each customer. See LPD MIO[23]: VADJ_FMC Power Rail for more details on the VADJ_FMC power rail.
Important: See the VEK280 board documentation ("Board Files" check box) for the XDC file.