LPDDR4 Component Memory

VEK280 Evaluation Board User Guide (UG1612)

Document ID
Release Date
1.1 English

[Figure 1, callout 2, 3, 4]

The VEK280 XCVE2802 device PL DDR memory interface performance is documented in the Versal Premium Series Data Sheet: DC and AC Switching Characteristics (DS959). The VEK280 board LPDDR4 component memory interfaces adhere to the constraints guidelines documented in the "PCB guidelines for Memory Interfaces" section of the Versal Adaptive SoC PCB Design User Guide (UG863). The VEK280 DDR4 component interface is a 40Ω impedance implementation. Other memory interface details are also available in the Versal Adaptive SoC Memory Resources Architecture Manual (AM007). For more memory component details, see the Micron MT53E512M32D1ZW data sheet on the Micron website. For the most current part number, see the Bill of Materials (BOM) located on the VEK280 Evaluation Board website. The detailed device connections for the feature described in this section are documented in the VEK280 board XDC file, referenced in Xilinx Design Constraints.

The VEK280 evaluation board hosts three LPDDR4 memory systems, each with a component configuration of 2x (1x32-bit component).

Figure 1. LPDDR4 Component Memory

XCVE2802 U1 has been configured with three triplet banks.

  • XPIO triplet 1 (banks 700/701/702)
  • XPIO triplet 2 (banks 703/704/705)
  • XPIO triplet 3 (banks 706/707/708)

Each support two independent 32-bit 2 GB component interfaces (4 GB per triplet). The VEK280 evaluation board uses the LPDDR4 memory components as follows:

  • Manufacturer: Micron
  • Part number: MT53E512M32D1ZW-046 WT:B (dual die LPDDR4 SDRAM)
  • Component description
    • 16 Gb (512 Mb x 32)
    • 1.1V 200-ball TFBGA
    • LPDDR4-2133