LPD MIO[23]: VADJ_FMC Power Rail

The VITA 57.4 FMC+ Industry Standard calls out not only specific connectors, but behaviors of the devices being connected. This creates a highly adaptable and flexible interface allowing a best fit for many industries and prototyping needs. While AMD strives to adhere to all standards providing customers with the best possible experience, in the case of the VEK280 evaluation and prototyping board, a compromise had to be made. Due to the I/O limitations on the XCVE2802-2MSEVSVH1760 package, there is limited VITA 57.4 compatibility. As the targeted use case for the VEK280 requires LPDDR4, a large quantity of I/O pins is used for the memory. This prevents the use of other features and capabilities for the designated feature set. To resolve this, pin-efficient layout and routing was selected for use with the LPDDR4. As a result, Banks 705 and 706 are tied to VADJ_FMC. VADJ_FMC_BUS is the non-adjustable voltage for the FMC connector (J51). VADJ_FMC and VADJ_FMC_BUS for the VEK280 is fixed to 1.5V at boot and, consequently, is non-compliant to the VITA 57.4 FMC+ Industry Standard. The power control of the VADJ_FMC power rail is managed by the power good and enable connection to U282.