The PS includes an integrated Aurora 64B/66B block that is dedicated for accessing the debug packet controller (DPC) via a high-speed GT-based interface. This protocol to access the DPC is the high-speed debug port (HSDP) protocol. The HSDP provides bidirectional access to the device from an external host debug/trace module, allowing for high-speed debug and trace operations. The SmartLynq+ module can be connected to the Aurora interface to access the HSDP in the Versal device. For more information, see the SmartLynq+ Module User Guide (UG1514). For information on the HSDP quad availability, see the Versal Adaptive SoC Technical Reference Manual (AM011)).
Note: The VEK280 evaluation board has additional
HSDP lanes provided for future System Controller use.
Note: The integrated HSDP Aurora interface is not
available in all Versal devices, which might support
HSDP using a soft Aurora solution. This interface requires additional configuration in
the Control, Interfaces, and Processing (CIPS) IP, a PL aurora implementation, and the
use of additional gigabit transceivers.