HDMI Clocking

VEK280 Evaluation Board User Guide (UG1612)

Document ID
Release Date
1.1 English

HDMI Source Clock

The VEK280 evaluation board includes a Renesas RC21008A (U299). This chip is used to source the 400 MHz FRL/DRU clock used as the reference for driving the Versal device (U1) logic and related circuitry for HDMI.

HDMI Clock Recovery

The HDMI circuitry includes a Renesas 8T49N241 frequency translator as a jitter attenuator. VE2802 can output a differential RX recovered clock (HDMI_RX_REFCLK) for jitter attenuation. The jitter-attenuated clock (HDMI_8T49N241_OUT) is routed as a reference clock to GTYP Bank 204. The 8T49N241 is used to generate the reference clock for the HDMI transmitter subsystem. When the HDMI transmitter is used standalone mode (FRL/TMDS) or pass-through mode (FRL), the 8T49N241 clock synthesizer (U362) operates in free running mode and uses an external oscillator as the reference. When the HDMI operation is in pass-through mode (TDMS), the 8T49N241 generates a jitter-attenuated reference clock to drive the HDMI transmitter subsystem with a phase-aligned version of the HDMI RX subsystem TMDS clock, so that they are phase aligned. The 8T49N241 is controlled by the HDMI 2.1 IP via I2C bus, HDMI_I2C_CTL.