[Figure 1, callout 45]
The VEK280 evaluation board has a fixed frequency very low jitter 3.3V LVDS oscillator (U374). The 156.25 MHz HSDP_156_25_REFCLK clock signal is connected to the XCVE2802 device U1 bank 106. At power-up, this clock defaults to an output frequency of 156.25 MHz.
- Fixed oscillator: CTS 626L15625I3T
- 156.25 MHz default
- LVDS differential output, total stability: ±25 ppm