Board Features

VEK280 Evaluation Board User Guide (UG1612)

Document ID
UG1612
Release Date
2024-01-31
Revision
1.1 English

The VEK280 evaluation board features are listed here. Detailed information for each feature is provided in Board Component Descriptions.

  • XCVE2802, VSVH2802 package
  • Form factor: see Board Specifications
  • Onboard configuration from:
    • USB-to-JTAG bridge
    • JTAG pod 2 mm 2x7 flat cable connector
    • microSD card (PS MIO I/F)
    • Quad SPI (QSPI)/eMMC (system controller I/F)
    • OSPI
  • Clocks
    • Versal device bank 702/5/6 RC21008A SYS_CLK_0/1/2 (DIMM) 200 MHz
    • Versal device bank GTY205/6 RC21008A_GTCLK1_OUT6/7 100 MHz
    • Versal device bank GTY106 RC21008A RC21008A_GTCLK1_OUT8 156.25 MHz
    • Versal device bank GTY106 626L15625 HSDP_156_25_REFCLK 156.25 MHz
    • Versal device bank GTY204 8T49N241 HDMI_8T49N241_OUT design dependent
    • Versal device bank GTY204 TMDS1204 HDMI_RCLK_OUT design dependent
    • Versal device bank 503 RC21008A PS_REF_CLK 33.3333 MHz
    • Versal device bank 503 RTC Xtal 32.768 kHz
  • Three pin-efficient mode LPDDR4 interfaces (2x32-bit 4 GB components each)
    • XPIO triplet 1 (banks 700, 701, 702)
    • XPIO triplet 2 (banks 703, 704, 705)
    • XPIO triplet 3 (banks 706, 707, 708)
  • PL FMCP HSPC (FMC+) connectivity
    • FMCP1 HSPC full LA[00:33] bus
  • PL GPIO connections
    • PL UART1 to FTDI
    • PL GPIO DIP switch (4-position)
    • PL GPIO LEDs (four)
    • PL GPIO pushbuttons (two)
    • PL SYSCTLR_GPIO[0:7]
    • PL 1588_GPIO[0:7, SMA_CLK I/O]
  • 32 PL GTYP transceivers (8 quads)
    • Not used (1, bank GTYP106)
    • System controller HSDP (1, banks GTYP106)
    • USB-C HSDP (1, banks GTYP106)
    • SFP28 (1, bank GTYP106)
    • PCIe Gen 4 (16, banks GTYP102-GTYP105)
    • FMCP1 HSPC DP (8, banks GTYP205, GTYP206)
  • PS PMC MIO connectivity
    • PS MIO[0:12]: boot configuration OSPI
    • PS MIO[13:25]: USB2.0
    • PS MIO[26:36, 51]: SD1 I/F
    • PS MIO[37]: ZU4_TRIGGER/CANFD0_INH (J406)
    • PS MIO[38]: CAN0_nSTB
    • PS MIO[39:41]: SYSMON_I2C
    • PS MIO[42:43]: UART0 to FTDI
    • PS MIO[44:47]: I2C1, I2C0
    • PS MIO[48], PS LPD MIO[0:11, 24:25]: GEM0 RGMII Ethernet RJ-45
    • PS MIO[11,49] and LPD MIO[12,13,20,23]: power enables
    • PS MIO[50] and LPD MIO[18:19]: PCIe status
    • PS LPD MIO [21:22]: optional fan interface
    • LPD MIO[23]: VADJ_FMC power rail
  • Security: PSBATT button battery backup
  • SYSMON header
  • Operational switches (power on/off, POR_B, boot mode DIP switch)
  • Operational status LEDs (INIT, DONE, PS STATUS, PGOOD)
  • Power management
  • System controller (XCZU4EG)

The VEK280 evaluation board provides a rapid prototyping platform using the XCVE2802-2MSEVSVH device. See the Versal Architecture and Product Data Sheet: Overview (DS950) for a feature set overview, description, and ordering information.