Packet Switching and the aiesimulator - 2025.2 English - UG1603

AI Engine-ML Kernel and Graph Programming Guide (UG1603)

Document ID
UG1603
Release Date
2025-11-26
Version
2025.2 English

The aiesimulator supports explicit packet switching. Consider the example of the previous graph that expects packet switched data from the PL. The data is split inside the AI Engine-ML and sent to four AI Engine kernels. On the output side the four kernel outputs merge into one output stream to the PL.

The input data file from the PL contains the packet switched data from the PL for the four AI Engine kernels in the previous example. It contains the data for different kernels, packet by packet. Each packet of data is for one iteration of an AI Engine kernel. The data format is as follows.

2415853568
0
1
2
3
4
5
6
TLAST
7
Here, 2415853568 is 0x8fff0000 in hex format. The five least significant bits are the packet ID, 0 in this case. The last data in the packet has the keyword TLAST, which denotes the last data for the input of the kernel.
Note: The packet header ID for the PL packet inputs to the aiesimulator must be an integer value.

You can construct the header for each packet manually, or write helper functions to generate the header. The AI Engine-ML compiler generates a packet switching report file Work/reports/packet_switching_report.json that lists the packet IDs used in the graph. Additionally, it also generates Work/temp/packet_ids_c.h and Work/temp/packet_ids_v.h header files. You can include these in your C or Verilog kernel code.