Overview - Overview - 2026.1 English - UG1603

The AMD Versal™ AI Core, Versal AI Edge Series, and Versal AI Edge Series Gen 2 deliver breakthrough AI inference acceleration with the AI Engine-Machine Learning (AI Engine-ML / AI Engine-ML v2) architecture. These devices are designed for a breadth of applications, including cloud for dynamic workloads and network for massive bandwidth, all while delivering advanced safety and security features. AI and data scientists, as well as software and hardware developers, can all take advantage of the high compute density to accelerate the performance of any application. Given its advanced tensor compute capability, AIE-ML and AIE-ML v2 devices are well-suited for highly optimized AI and ML applications.

The AIE-ML / AIE-ML v2 devices contain a two dimensional array of AI Engines. TheseAI Engines are based on very-long instruction word (VLIW) processors, equipped with single instruction multiple data (SIMD) vector units. This makes them well-suited for highly optimized tasks for compute-intensive applications, specifically AI technology such as machine learning (ML).

The AI Engine array supports three levels of parallelism:

Instruction Level Parallelism (ILP)

Through the VLIW architecture allowing multiple operations to be executed in a single clock cycle.

SIMD

Through vector registers allowing multiple computations to be performed in parallel.

Multicore

Through the AI Engine array, allowing several AI Engine cores to execute in parallel.

Instruction-level parallelism includes a scalar operation, one move, two vector reads (loads), one vector write (store), and one vector instruction that can be executed—in total, a 6-way VLIW instruction per clock cycle. Data-level parallelism is achieved via vector-level operations where multiple sets of data can be operated on a per-clock-cycle basis.

Each AI Engine contains both a vector and scalar processor, dedicated program memory, local 64 KB data memory, access to local memory in itself and in three neighboring AI Engines. It also has access to DMA engines and AXI4 interconnect switches to communicate via streams to other AI Engines, the programmable logic (PL), or the DMA.

Refer to the Versal Adaptive SoC AIE-ML Architecture Manual (AM020) for specific details on the AI Engine-ML array and interfaces. Refer to the Versal Adaptive SoC AIE-ML v2 Architecture Manual (AM027) for specific details on the AI Engine-ML v2 array and interfaces.

You can compile most standard C code for the AI Engine. However, you might need to restructure the code to take full advantage of the parallelism provided by the hardware. The power of an AI Engine is in its ability to execute a multiply-accumulate (MAC) operation using two vectors, load two vectors for the next operation, store a vector from the previous operation, and increment a pointer or execute another scalar operation in each clock cycle. Specialized functions called intrinsics allow you to target the AI Engine vector and scalar processors and provide implementation of several common vector and scalar functions, so you can focus on the target algorithm. In addition to its vector unit, an AI Engine also includes a scalar unit which it uses for all standard C-code programs.

An AI Engine program uses a C++ data-flow graph (adaptable data flow graph) specification. You can compile and execute this specification using the AI Engine compiler. An adaptive data flow (ADF) graph application consists of nodes and edges where nodes represent compute kernel functions, and edges represent data connections. You can compile kernels in the application to run on the AI Engine. These kernels are the fundamental building blocks of an ADF graph specification.

An ADF graph is a Kahn process network with the AI Engine kernels operating in parallel. AI Engine kernels operate on data streams as well as buffers. These kernels consume blocks of input data and produce blocks of output data. Kernels can also have static data or runtime parameter (RTP) arguments that can be either asynchronous or synchronous.

The following figure shows the conceptual view of the ADF graph and its interfaces with the processing system (PS), programmable logic (PL), and DDR memory. It consists of the following components:

AI Engine

Each AI Engine is a VLIW processor containing a scalar unit, a vector unit, two load units, and a single store unit.

AI Engine Kernel

C/C++ kernels running in an AI Engine-ML.

ADF Graph

An ADF graph is a Kahn process network with a single or multiple AI Engine kernels connected by data streams and/or buffers. It interacts with the PL, global memory, and PS with specific constructs such as:

• PLIO (the port attribute in the graph which makes stream connections to or from the programmable logic)
• GMIO (the port attribute in the graph which makes external memory-mapped connections to or from the global memory)
• RTP

The AIE-ML / AIE-ML v2 device consists of one or two rows of memories in the AI Engine-ML array accessible from the AXI4-Stream network. For information on the memory tile access, refer to AI Engine-ML Memory Tile Access.

Chapters 2 to 5 of this document focus on AI Engine kernel programming. These chapters cover aspects beyond single kernel programming such as data communication between kernels. These are essential concepts for partitioning the application into multiple kernels to achieve the required throughput.

Chapters 6 to 14 of this document focus on AI Engine graph programming construction. This includes the following:

• Types of data communication between kernels
• Controlling the AI Engine graph via a host application
• Advanced graph programming constructs