Deterministic Merge to Memory Tile - 2024.1 English

AI Engine-ML Kernel and Graph Programming Guide (UG1603)

Document ID
UG1603
Release Date
2024-06-06
Version
2024.1 English

When memory tile DMA channel or routing resource is limited, you can reuse the memory tile DMA channel to merge multiple packet streams into the memory tile.

The adf::pktorderedmerge<N> construct can be used to merge multiple data sources into a single destination in a deterministic order. To use packets for memory tile, add packet_port_id to the tiling parameters. Tiling parameters can also be chained together to support different packet IDs for the same port.

The following is an example graph code where the packet merges multiple buffers to the memory tile in a deterministic order:

kernel sourcekernel[4], sink;
shared_buffer<int32> mtx;
adf::pktorderedmerge<4> merge;
......
mtx = shared_buffer<int32>::create({512}, 1, 1);
merge = adf::pktorderedmerge<4>::create();

//connecting from kernels to packet merge, and from merge to shared buffer
for(int i=0; i<4; i++)
{
    connect(sourcekernel[i].out[0], merge.in[i]);
}
connect(merge.out[0], mtx.in[0]);

//chain multiple tiling parameters together. Tiling parameters will be executed one by one.
std::vector<adf::access_pattern> v;
for(int i=0; i<4; i++)
{
    //Each packet writes 128 elements sequentially
    v.push_back(adf::tiling({ .buffer_dimension = { 512 }, .tiling_dimension = { 128 }, .offset = { 128 * i }, .tile_traversal = { { .dimension = 0,.stride = 128, .wrap = 1 } }, .packet_port_id = i })); 
}
write_access(mtx.in[0]) = v;

adf::tiling_parameters params1 = { .buffer_dimension = { 512 }, .tiling_dimension = { 32 }, .offset = { 0 }, .tile_traversal = { { .dimension = 0,.stride = 32, .wrap = 16 } } };
read_access(mtx.out[0]) = {tiling(params1)}; 
connect(mtx.out[0], sink.in[0]);
connect(sink.out[0], out.in[0]);

The example graph view is as follows:

Figure 1. Packet Merge to Memory Tile Graph View