You can configure input_gmio or output_gmio objects to
make external memory-mapped connections to or from the global memory. These
connections are made between an AI Engine graph and the logical global memory ports of a
hardware platform design. The platform can be a base AMD platform or a custom platform exported from the Vivado tools as a Xilinx support archive (XSA)
package.
AI Engine-ML tools support mapping the
input_gmio
or
output_gmio port to the tile DMA, one to one. It
does not support mapping multiple input_gmio/output_gmio ports to one
tile DMA channel. Each device supports a limited number of input_gmio/output_gmio ports. For
example, the XCVE2802 device on the VEK280 board has 12 AI Engine-ML to NoC master units (NMU) in total. For each AI Engine-ML to NMU, it supports two MM2S and two S2MM
channels. So, there can be at most 24 AI Engine-ML GMIO inputs, and 24 AI Engine-ML GMIO outputs.
The existing hardware platform can further limit support.
While developing data flow graph applications on top of an existing hardware platform, you need to know what global memory ports are exported by the underlying XSA and their functionality. In particular, the XSA records input or output ports exposed on the platform. These can be viewed as a logical architecture interface.