Each column of the AI Engine-ML / AI Engine-ML v2 array has one or two memory tiles depending on the device. These are located between the column and the AIE-ML / AIE-ML v2 interface tile.
Each AIE-ML / AIE-ML v2 memory tile has 512 KB of ECC protected memory divided in banks. Each bank allows one read or one write every cycle and can be accessed by read and write interfaces. The AXI4-Stream network provides access to this memory.
| Component | AIE-ML | AIE-ML v2 |
|---|---|---|
| No. of Memory Banks | 16 | 8 |
| Bank size | 128-bit x 2k words | 256-bit x 2k words |
| Read Interface | 9 | 10 |
| Write Interface | 9 | 10 |
Each AIE-ML / AIE-ML v2 memory tile contains the following:
- Six Memory to Stream DMAs (MM2S)
- Six Stream to Memory DMAs (S2MM)
- Access to East and West Memory Tiles, for a total of 1.5 MB addressable memory
- 5D addressing (including iteration-offset)
- Zero-padding insertion features on MM2S DMAs
- Out-of-order packets and finish on TLAST features on S2MM DMAs
The memory in the memory tile supports configurable bank
interleaving. The banks can be addressed in linear or interleaved mode. Data can
also be accessed with the AXI-MM interface.
The AXI4-Stream and AXI4 memory mapped network provide access to this memory.
Data are received through the 6x S2MM DMAs as well as 2x S2MM DMA
from west and east MEM Tile neighbor and from the AXI-MM interface. Data are sent through the 6x MM2S DMAs as well as 2x
MM2S to west and east neighbor MEM Tiles and to the AXI-MM interface.
Local DMAs are programmed through buffer descriptors (48) and managed by semaphores locks (64x 6-bit values).
Memory access is done though four dimensional addressing, the first three being potentially subject to zero-padding. A mechanism of iteration and offset is also integrated making the overall access equivalent to a 5D addressing. For details on address generation, refer to Memory and DMA Programming.