AI Engine-ML/Programmable Logic Integration - 2024.1 English

AI Engine-ML Kernel and Graph Programming Guide (UG1603)

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2024.1 English

When you are ready to consider interfacing to the programmable logic (PL), you need to make a decision on the platform you want to interface with. A platform is a fully contained image that defines both the hardware (XSA) as well as the software (bare metal, Linux, or both). The XSA contains the hardware description of the platform, which is defined in the AMD Vivado™ Design Suite, and the software is defined with the use of a bare-metal setup, or a Linux image defined through PetaLinux. Depending on the needs of your application you might decide to use an example reference platform provided by AMD, or a custom platform created by your organization.

AMD recommends interfacing to the PLIO port attributes which represent external stream connections that cross the AI Engine-ML-PL boundary. PLIO represents an ADF graph interface to the PL. This PL could be, for example, a PL kernel, a platform IP representing a signal source or sink, or it could be a data mover to interface the ADF graph to memory.

Alternatively interface connections can also be GMIO port attributes which represent external memory-mapped connections to or from the global memory. Further details on these attributes can be found in Graph Programming Model.

Note: The AI Engine Engine Graph with PL kernels (HLS or RTL kernels) can be co-simulated using the Vitis Hardware Emulation flow.