AI Engine Data Memory - AI Engine Data Memory - 2026.1 English - UG1603

Each AI Engine has 16 KB of program memory, which allows storing 1024 instructions of 128-bit each. The AI Engine instructions are 128 bit (maximum) wide. They support multiple instruction formats, as well as variable length instructions to reduce the program memory size. Many instructions outside of an optimized inner loop can use the shorter formats.

Each AI Engine tile has 64 KB of data memory for AIE-ML and AIE-ML v2, divided into eight single-port memory banks.

Each AI Engine can access its own data memory in addition to those in adjacent AI Engine tiles in the north, south, and west neighbors. This allows a single AIE-ML / AIE-ML v2 to access a total of 256 KB of data memory. The stack is placed in data memory.

The default sizes for the stack and heap are 1 KB each. The compiler can automatically estimate and adjust the heap size at the default optimization level; the stack size is not automatically estimated and must be specified. Stack size and heap size can be changed using compiler options or constraints in the source code. When the tool-computed heap size is greater than the explicitly specified value, the compiler fails. Refer to the AI Engine Tools and Flows User Guide (UG1076) for more information about stack and heap size usage.

In a logical representation, you can consider the 256 KB memory as one contiguous 256 KB block or four 64 KB blocks. Each block can be divided into four odd and four even banks. One even bank and one odd bank interleave to comprise a double bank. AI Engines on the edges of the AI Engine array have fewer neighbors and correspondingly less memory available.

Each AI Engine has three address generation units (AGUs) or ports. You can use the AGUs in an AI Engine for address generation for vector load/store operations.

Each memory port operates in vector register mode or scalar register mode for devices with AIE-ML. The ports are created by an even and odd pairing of the memory banks. The 8-bit and 16-bit stores are implemented as read-modify-write instructions (minimum memory access granularity is 32 bits). Concurrent operation of all three ports (Address Generation Units) is supported if each port accesses a different bank.

Data stored in memory is in little endian format.

Each AI Engine has a DMA controller which comprises two separate modules: S2MM and MM2S:

• S2MM to store stream data to memory
• MM2S to write the contents of the memory to a stream.

Both S2MM and MM2S have two independent data channels.