The Xilinx™ design constraints (XDC) file template for the VPK180 board provides for designs targeting the VPK180 evaluation board. Net names in the constraints listed correlate with net names on the latest VPK180 evaluation board schematic. Identify the appropriate pins and replace the net names with net names in the user RTL.
See the Vivado Design Suite User Guide: Using Constraints (UG903) for more information.
The HSPC FMCP connector J51 is connected to the Versal device U1 banks powered by the variable voltage VADJ_FMC. Because different FMC cards implement different circuitry, the FMC bank I/O standards must be uniquely defined by each customer. See LPD MIO[23]: VADJ_FMC Power Rail for more details on the VADJ_FMC power rail.