The VPK180 board provides fixed and variable clock sources for the XCVC1802 U1 device and other function blocks. The following table lists the source devices for each clock.
| Ref. Des. | Feature | Notes | Schematic Page |
|---|---|---|---|
| U248 | DDR4 DIMM CLK, 200 MHz, 3.3V LVDS, 0x60
|
Skyworks/Silicon Labs 570BAB000299DG | 3 |
| U3 | DDR4 DIMM CLK, 200 MHz, 3.3V LVDS, 0x60
|
Skyworks/Silicon Labs 570BAB000299DG | 4 |
| U4 | DDR4 DIMM CLK, 200 MHz, 3.3V LVDS, 0x60
|
Skyworks/Silicon Labs 570BAB000299DG | 5 |
| U312 | HSDP System Controller REFCLK1, 156.25 MHz, 3.3V LVDS | CTS 626L15625I3T | 8 |
| U313 | HSDP System Controller REFCLK1, 156.25 MHz, 3.3V LVDS | CTS 626L15625I3T | 8 |
| U32 | Adaptive SoC U1 REF CLK, 33.33 MHz, 1.8V CMOS, 0x5D
|
Skyworks/Silicon Labs 570JAC000900DGR | 54 |
| U298 | Adaptive SoC U1 GTM CLK, 156.25 MHz, 1.8V LVDS, 0x09
|
Renesas RC21008A065GND | 61 |
| U299 | Adaptive SoC U1 GTM CLK, 156.25 MHz, 1.8V LVDS, 0x09
|
Renesas RC21008A065GND | 62 |
| U219 | IEEE-1588 eCPRI CLK, various, 3.3V, 0x5B
|
Renesas/IDT 8A34001E-000AJG8 | 90 |
The detailed device connections for the feature described in this section are documented in the VPK180 board XDC file, referenced in Xilinx Design Constraints.