References - References - 2025.2 English - UG1580

1. Zynq UltraScale+ MPSoC Verification IP Data Sheet (DS940)
2. Zynq 7000 SoC Verification IP Data Sheet (DS941)
3. Zynq UltraScale+ MPSoC: Embedded Design Tutorial (UG1209)
4. Zynq 7000 SoC: Embedded Design Tutorial (UG1165)
5. Triple Modular Redundancy (TMR) LogiCORE IP Product Guide (PG268)
6. UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150)
7. Zynq 7000 SoC Technical Reference Manual (UG585)
8. Zynq 7000 SoC and 7 series Devices Memory Interface Solutions (UG586)
9. Vitis Unified Software Platform Documentation
10. Zynq 7000 SoC Software Developers Guide (UG821)
11. Vivado Design Suite Tcl Command Reference Guide (UG835)
12. Zynq 7000 SoC Packaging and Pinout Product Specifications (UG865)
13. Vivado Design Suite User Guide: Design Flows Overview (UG892)
14. Vivado Design Suite User Guide: Using the Vivado IDE (UG893)
15. Vivado Design Suite User Guide: System-Level Design Entry (UG895)
16. Vivado Design Suite User Guide: Synthesis (UG901)
17. Vivado Design Suite User Guide: Using Constraints (UG903)
18. Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)
19. ISE to Vivado Design Suite Migration Guide (UG911)
20. Zynq 7000 SoC PCB Design Guide (UG933)
21. Vivado Design Suite Tutorial: Embedded Processor Hardware Design (UG940)
22. UltraScale Architecture Libraries Guide (UG974)
23. Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
24. Vivado Design Suite Tutorial: Designing IP Subsystems Using IP Integrator (UG995)
25. Zynq UltraScale+ Device Packaging and Pinouts Product Specification User Guide (UG1075)
26. Zynq UltraScale+ Device Technical Reference Manual (UG1085)
27. Vivado Design Suite User Guide: Creating and Packaging Custom IP (UG1118)
28. Zynq UltraScale+ MPSoC: Software Developers Guide (UG1137)