The AMD Vivado™ IDE IP integrator is a powerful tool that lets you stitch together a processor-based system.
The MicroBlaze embedded processor is a reduced instruction set computer (RISC) core, optimized for implementation in AMD Field Programmable Gate Arrays (FPGAs).
The following figure shows a functional block design of the MicroBlaze core.
The MicroBlaze processor is highly configurable. You can select a specific set of features required by your design. The fixed feature set of the processor includes:
- Thirty-two 32-bit general purpose registers
- 32-bit instruction word with three operands and two addressing modes
- 32-bit address bus
- Single issue pipeline
In addition to these fixed features, the MicroBlaze processor has parameterized values that allow selective enabling of additional functionality.
See the MicroBlaze Processor Reference Guide (UG984) for more information.
Additionally, the floating point unit (FPU) is extended to support double precision.
Also, refer Triple Modular Redundancy (TMR) LogiCORE IP Product Guide (PG268) which provides soft error detection, correction, and recovery for AMD devices. The guide describes the IP cores that are part of the solution, and explains typical use cases.