MicroBlaze Configuration Wizard: Cache Page - 2024.1 English

The following figure shows the Cache options page for the MicroBlaze configuration.

Figure 1. Cache Options Page of the MicroBlaze Configuration Wizard

• Enable Instruction Cache: Uses this cache only when it is also enabled in software by setting the instruction cache enable (ICE) bit in the machine status register (MSR).

  The Instruction Cache configurable options are:

  • Size in Bytes: Specifies the size of the instruction cache if C_USE_ICACHE is enabled. Not all architectures permit all sizes.
  • Line Length: Select between 4, 8, or 16 word cache line length for cache miss-transfers from external instruction memory.
  • Base Address: Specifies the base address of the instruction cache. This parameter is used only if C_USE_ICACHE is enabled.
  • High Address: Specifies the high address of the instruction cache. This parameter is used only if C_USE_ICACHE is enabled.
  • Enable Writes: When enabled, one can invalidate instruction cache lines with the wic instruction. This parameter is used only if C_USE_ICACHE is enabled.
  • Use Cache for All Memory Accesses: When enabled, uses the dedicated cache interface on MicroBlaze is for all accesses within the cacheable range to external instruction memory, even when the instruction cache is disabled.

    Otherwise, the instruction cache uses the peripheral AXI for these accesses when the instruction cache is disabled.

    When enabled, an external memory controller must provide only a cache interface MicroBlaze instruction memory. Enable this parameter when using AXI Coherency Extension (ACE).

  • Use Distributed RAM for Tags: Uses the instruction cache tags to hold the address and a valid bit for each cache line. When enabled, the instruction cache tags are stored in Distributed RAM instead of block RAM. This saves block RAM, and can increase the maximum frequency.
  • Data Width: Specifies the instruction cache bus width when using AXI Interconnect. The width can be set to:
    • 32-bit: Bursts are used to transfer cache lines for 32-bit words depending on the cache line length,
    • Full Cache line: A single transfer is performed for each cache line, with data width 128, 256, or 512 bits depending on cache line length
    • 512-bit: Performs a single transfer, but uses only 128 or 256 bits, with 4 or 8 word cache line lengths.

    The two wide settings require that the cache size is at least 8 KB, 16KB, or 32KB depending upon cache line length. To reduce the AXI interconnect size, this setting must match the interconnect data width. In most cases, you can obtain the best performance with the wide settings.

    This setting is not available with area optimization, AXI Coherency Extension (ACE), or when you enable fault tolerance.

  • Number of Streams: Specifies the number of stream buffers used by the instruction cache. A stream buffer is used to speculatively pre-fetch instructions, before the processor requests them. This often improves performance, because the processor spends less time waiting for instruction to be fetched from memory.

    To be able to use instruction cache streams, do not enable area optimization or AXI Coherency Extension (ACE).

  • Number of Victims: Specifies the number of instruction cache victims to save. A victim is a cache line that is evicted from the cache. If no victims are saved, all evicted lines must be read from memory again, when they are needed. By saving the most recent lines, they can be fetched much faster, thus improving performance.
  Recommended: It is possible to save 2, 4, or 8 cache lines. The more cache lines that are saved, the better performance becomes. The recommended value is 8 lines.
  Note: To be able to use instruction cache victims, do not enable area optimization or AXI Coherency Extension (ACE).
• Enable Data Cache: Uses this cache only when it is also enabled in software by setting the data cache enable (DCE) bit in the machine status register (MSR).

  Data Cache Features:

  • Size in Bytes: Specifies the size of the data cache if C_USE_DCACHE is enabled. Not all architectures permit all sizes.
  • Line Length: Select between 4, 8, or 16 word cache line length for cache miss-transfers from external memory.
  • Base Address: Specifies the base address of the data cache. This parameter is used only if C_USE_DCACHE is enabled.
  • High Address: Specifies the high address of the data cache. This parameter is used only if C_USE_DCACHE is enabled.
  • Enable Writes: When enabled, one can invalidate data cache lines with the wdc instruction. This parameter is used only if C_USE_DCACHE is enabled.
  • Use Cache for All Memory Accesses: When enabled, uses the dedicated cache interface on MicroBlaze is for all accesses within the cacheable range to external memory, even when the data cache is disabled.

    Otherwise, the data cache uses the peripheral AXI for these accesses when the data cache is disabled.

    When enabled, an external memory controller must provide only a cache interface MicroBlaze data memory. Enable this parameter when using AXI Coherency Extension (ACE).

  • Use Distributed RAM for Tags: Uses the data cache tags to hold the address and a valid bit for each cache line. When enabled, the data cache tags are stored in Distributed RAM instead of block RAM. This saves block RAM, and can increase the maximum frequency.
  • Data Width: Specifies the data cache bus width when using AXI Interconnect. The width can be set to:
    • 32-bit: Bursts are used to transfer cache lines for 32-bit words depending on the cache line length
    • Full Cache line: A single transfer is performed for each cache line, with data width 128, 256, or 512 bits depending on cache line length
    • 512-bit: Performs a single transfer, but uses only 128 or 256 bits, with 4 or 8 word cache line lengths
    The two wide settings require that the cache size is at least 8 KB, 16KB, or 32KB depending upon cache line length. To reduce the AXI Interconnect size, this setting must match the interconnect data width. In most cases, you can obtain the best performance with the wide settings.

    Note: This setting is not available with area optimization, AXI Coherency Extension (ACE), or when you enable fault tolerance.
  • Number of Streams: Specifies the number of stream buffers used by the instruction cache. A stream buffer is used to speculatively pre-fetch instructions, before the processor requests them. This often improves performance, because the processor spends less time waiting for instuctions to be fetched from memory.

    To be able to use instruction cache streams, do not enable area optimization for AXI Coherency Extension (ACE).

  • Enable Write-back Storage Policy: This parameter enables use of a write-back data storage policy. When this policy is in effect, the data cache only writes data to memory when necessary, which improves performance in most cases. With write-back enabled, data is stored by writing an entire cache line. Using write-back also requires that the cache is flushed by software when appropriate, to ensure that data is available in memory; for example, when using direct memory access (DMA). When not enabled, a write-through policy is used, which always writes data to memory immediately.
  Tip: When the MMU is enabled, setting this parameter allows individual selection of storage policy for each TLB entry.
  • Number of Victims: Specifies the number of data cache victims to save. A victim is a cache line that is evicted from the cache. If no victims are saved, all evicted lines must be read from memory again, when they are needed. By saving the most recent lines, they can be fetched much faster, thus improving performance.
  Recommended: It is possible to save 2, 4, or 8 cache lines. The more cache lines that are saved, the better performance becomes. The recommended value is 8 lines.
  Note: To be able to use data cache victims, do not enable area optimization or AXI Coherency Extension (ACE).