General Settings - 2025.1 English - UG1579

If a pre-defined template is not used, you can select the options from the pages, which are available for fine-tuning the MicroBlaze™ V processor, based on the design needs. As you position the mouse over these different options, a tooltip informs you what the particular option means. The following bullets detail these options:

• Select implementation optimization: When set to:
  • PERFORMANCE: Implementation is selected to balance computational performance and achievable frequency using a five-stage pipeline.
  • AREA: Implementation is selected to optimize area, using a three-stage pipeline with lower instruction throughput.
  • FREQUENCY: Implementation is selected to optimize MicroBlaze frequency, using an eight-stage pipeline.
  Recommended: It is recommended to select AREA optimization on architectures with limited resources such as AMD Artix™ 7 or Spartan 7 devices. Selecting FREQUENCY optimization is recommended to reach system frequency targets, particularly with cache-based external memory, and/or large LMB memory. However, if performance is critical, do not select AREA or FREQUENCY optimization because some instructions require additional clock cycles to execute.
  Note: You cannot use the Memory Management Unit (MMU), Branch Target Cache, Instruction Cache Streams, Instruction Cache Victims, Data Cache Victims, and AXI Coherency Extension (ACE) with area optimization.
• Enable MicroBlaze Debug Module Interface: Enable debug to be able to download and debug programs using Xilinx System Debugger (XSDB).
  Recommended: Unless area resources are very critical, it is recommended that debugging always is enabled.
• Use Instruction and Data Caches : You can use MicroBlaze with optional instruction and data caches for improved performance when executing code that resides outside the LMB address range. The caches have the following features:
  • Direct mapped (1-way associative)
  • User selectable cacheable memory address range
  • Configurable cache size
  • Caching over AXI4 interfaces (M_AXI_IC and M_AXI_DC)
  • Option to use 4, 8, or 16 word cache line
  • Cache on and off controlled using bits in the MSR
  • Optional WIC and WDC instructions to invalidate, clear or flush instruction cache lines
  • Optional parity protection, invalidates cache lines if Block RAM bit error is detected
  • Optional data width selection to either use 32-bit, an entire cache line, or 512-bit
  Note: Activating caches significantly improves performance when using external memory. Ensure to select small cache sizes to reduce resource usage.
• Enable Exceptions: Enables exceptions when using an operating system with exception support, or when explicitly adding exception handlers in a standalone program.
• Use Memory Management: Enables Memory Management if planning to use an operating system such as Linux with support for virtual memory of memory protection.
  Note: When you enable area optimized MicroBlaze or stack protection, the Memory Management Unit is not available.
• Enable Discrete Ports: Enables discrete ports on the MicroBlaze instance, which is useful for:
  • Generating software breaks (Ext_BRK, Ext_NM_BRK)
  • Managing processor sleep and wakeup (Sleep, Hibernate, Suspend, Wakeup, Dbg_Wakeup)
  • Handling debug events (Debug_Stop, MB_Halted)
  • Signaling error when using fault tolerance (MB_Error)
  • Pausing the processor (Pause, Pause_Ack, Dbg_Continue)
  • Setting reset mode (Reset_Mode)