Some AMD Zynq™ UltraScale+™ RFSoCs include highly flexible Soft-Decision Forward Error Correction (SD-FEC) blocks for decoding and encoding data as a means to control errors in data transmission over unreliable or noisy communication channels. The SD-FEC blocks support low-density parity check (LDPC) decode/encode and Turbo decode for use in 5G wireless, backhaul, DOCSIS, and LTE applications.
You can use a total of eight cores for error as shown in the table of the SD-FEC page.
Figure 1. SD-FEC Table
Use the following inputs to estimate the power:
- Mode
- The following SD-FEC configuration modes are available for selection:
- LDPC Encode
- LDPC Decode
- Turbo Decode
- Standard
- Specify the standard used for a particular application. You can select any of
the following standards:
- 5G
- DOCSIS
- Wi-Fi
- Custom
- LTE for Turbo Decode
- Throughput Utilization
- Specify the throughput utilization of the SD-FEC cores used. This is instance throughput relative to maximum throughput supported by the core.
- Clock
- Specify the clock for the SD-FEC core. After providing necessary inputs, PDM displays the estimated power for the VCCINT and VCCSDFEC power supplies.