The AMD Zynq™ UltraScale+™ MPSoC family of products integrates a feature rich 64-bit quad core Arm Cortex® -A53 and dual core Arm Cortex® -R5F based processing system (PS) and AMD programmable logic (PL) AMD UltraScale™ architecture in a single device.
The PS can be configured in the following PS Power Modes:
- User Configuration
- This mode allows the full configuration the of PS. For PS Dynamic power estimation the Power Mode should be first set to User Config.
- Power Down Mode
- Selection of this mode leads to complete power down of PS leading to PS dynamic power of 0. No configuration is permitted in this mode.
Figure 1. Summary and Power Management Control
Low Power Domain
Low Power Domain (LPD) can be configured from the LPD tables as shown in the following figure. The LPD consists of the following:
- Dual core Arm Cortex-R5F
- Tightly-Coupled Memory (TCM) and On Chip Memory (OCM)
- LPD Interconnect
- CSU (Configuration Security Unit)
- PMU (Platform Management Unit)
- LPD PLLs and IOs
- LPD AXI Interfaces
Figure 2. Low Power Domain
Figure 3. LPD -Bank 500
Full Power Domain
Full Power Domain (FPD) can be configured from the FPD tables as shown in the following figure. The full power domain consists of:
- 64-bit quad-core Arm Cortex with L2 Cache
- Mali-400 MP GPU
- FPD Interconnect
- FPD Hard Memory Controller (DDR)
- FPD GTR (For IOs that need GT)
- FPD Interfaces
Figure 4. Full Power Domain
