Power Rail Consolidation - 2025.2 English - UG1556

Power Design Manager User Guide (UG1556)

Document ID
UG1556
Release Date
2025-11-20
Version
2025.2 English

PDM models power rail consolidation based on selected power delivery solution. PDM supports following two options for power delivery solution.

Full Power Management

This is the recommended solution. It allows for full power management, which means that an individual rail can be sequenced on and off as required to reduce power.

SoC Mode

In Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 devices, SoC mode is a hybrid approach that replaces the Full Power Management mode used in earlier device families. This mode consolidates the System, LPD, and FPD into a single configuration. By reducing the number of required regulators, SoC mode simplifies power design while maintaining flexibility for power management.

Minimum Rails

This mode allows to consolidate power supply while maintaining the required sequence and voltage specification for every rail.

Only Artix UltraScale+, Kintex UltraScale+ and Virtex UltraScale+ devices have Minimum Rails option support. Other devices support both Full power management and Minimum Rails options.

Figure 1. Power Rail Consolidation
Figure 2. Power Rail Characteristics for Rail Consolidation

Based on the power rail consolidation selection, the following images change to show the connectivity based on the targeted device.

Depending on the device family, the following rail consolidation modes may be available:

  • Full Power Management
  • SoC Mode
  • Minimum Rails

These options change automatically based on the VCCINT voltage of the targeted device or when the PS overdrive is used in a low voltage device. The following image shows the Power Management diagram when Full Power Management is chosen.

Figure 3. Power Delivery and Sequencing for Rail Consolidation

The following image shows the Power Management diagram when you select SoC mode for Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 devices.

Figure 4. SoC Mode