Multiport RAM - 2024.2 English - UG1556

Power Design Manager User Guide (UG1556)

Document ID
UG1556
Release Date
2024-11-18
Version
2024.2 English

The Multiport RAM (MPRAM) block is supported only for AMD Versalâ„¢ VP10x2 devices in the Versal Premium family. MPRAM block has up to eight memory units, each of which is made up of 20 single ported memory macros of 2048x128b. Therefore, the size of each memory unit is up to 5 MB. A memory unit consists of two local read and one local write (128-bit) ports, which can only access the associated memory unit.

Refer to Multiport RAM LogiCORE IP Product Guide (PG415) for more information.

To estimate power of MPRAM block in the PDM tool, you should configure the following parameters.

Interface Clock Frequency
It is the interface clock frequency for MPRAM. The internal core clock is always doubled, and hence, memory units run twice the rate of the interface clock.
Toggle Rate
This is average data toggle rates across all interface to RAMs. It ranges between 0%-100%.
Average Active Duty Cycle
It is the average active duty cycle across the RAM units, expressed in percentage. Each RAM interface contributes to 50% activity. Global interfaces only access one RAM at a time.
Number of RAMs
It is the required number of memory. Ranges from 1-8.
Figure 1. PDM MPRAM