The Hard IP Block setting allows you to calculate the power associated with the following AMD UltraScale+™ device integrated IP blocks:
- PCIe
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The integrated PCI Express core is a reliable, high-bandwidth, scalable serial interconnect. Select PCIe when using hard GEN1, GEN2, GEN3 or GEN4 PCIe interface with GTs. Select PCIe_500 when using hard GEN3/GEN4 PCIe interface operating with an optional 500 MHz core clock frequency.
- 100 G Ethernet
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The integrated block for 100 Gb/s Ethernet (100 G MAC) provides a high performance, low latency 100 Gb/s Ethernet port that allows for a wide range of user customization and statistics gathering. If your design uses the integrated block for 100 Gb/s Ethernet, select CMAC. Select CMAC-Low when you use low data toggle rate or CMAC-High for worse case data toggle rate. For detailed information on this IP block, see the UltraScale Devices Integrated 100G Ethernet LogiCORE IP Product Guide (PG165).
- Interlaken
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The integrated block for Interlaken is a scalable chip-to-chip interconnect protocol designed to enable the following: The lane logic only mode allows each serial transceiver to be used to build a fully featured Interlaken interface. In devices with 48 serial transceivers, up to 600 Gb/s of total throughput can be sustained. The protocol logic supported in each integrated IP core scales up to 150 Gb/s.
If your design uses the integrated block for Interlaken, select ILKN. Select ILKN-Low when you use low TX data toggle rate or ILKN-High for worse case data toggle rate. For detailed information on this IP block, see the Integrated Interlaken up to 150G LogiCORE IP Product Guide (PG169).
These IP blocks are designed to be combined with GTH or GTY transceivers to implement an integrated solution. You can use the Transceiver Configuration wizard to combine the appropriate GTH or GTY transceiver configuration with an integrated hard IP block. To open the Transceiver Configuration wizard, click the Create GTH button at the top of the GTH page. Or click the Create GTY button at the top of the GTY page.
- LPDDRMC
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AMD Spartan™ UltraScale+™ feature hardened memory controllers that are designed to support LPDDR4x and LPDDR5 memory interfaces. You can configure the LPDDRMC using the Create LPDRMC wizard option in Hard IP Blocks. Creating a LPDDRMC using the wizard populates the required DDR I/Os in I/O page. The following figure shows LPDDRMC Configuration wizard.
Figure 1. LPDDRMC Wizard - PCIe4CE
- PCIe4CE block provides a high-performance PCI Express port that allows for a wide range of user customization. It supports up to Gen4 data rate (16 Gb/s). You can populate the PCIe4CE using create GT wizard.