Terms and Acronyms

Alveo X3522 User Guide (UG1523)

Document ID
UG1523
Release Date
2023-08-25
Revision
1.4 English

The following table lists terms used in the guide and their definitions.

Table 1. Terms and Definitions
Term Definition
AN, AN/LT

Auto-negotiation / Link Training.

Sets the speed of an Ethernet link.

ARP

Address Resolution Protocol.

Maps IP addresses to MAC addresses.

BASE-R FEC

A type of Forward Error Correction also known as Firecode.

CPU

Central Processing Unit.

CTPIO

Cut Through Programmed Input/Output.

TX packets are streamed directly from the PCIe interface to the adapter port to deliver lowest TX latency.

DAC cable

Direct Attach Copper cable.

DDR

Double Data Rate memory.

Transfers data on rising and falling edges of the clock.

DSFP

Dual Small Form-factor Pluggable.

A 2-channel (dual) network transceiver design that is compatible with SFP+/ SFP28 transceivers. See the DSFP MSA website.

ECC

Error Correction Code.

EFCT

The native interface for an X3522.

FCS

Frame Check Sequence.

Error-detecting code added to an Ethernet frame.

FEC

Forward Error Correction.

Employs redundancy in channel coding as a technique used to reduce bit errors.

FPGA

Field Programmable Gate Array.

A semiconductor device that is based around a matrix of configurable logic blocks connected via programmable interconnects.

IRQ

Interrupt Request.

LAN

Local Area Network.

MCDI

Management CPU Driver Interface.

Passes messages and events between the host driver and the X3522 firmware.

MTU

Maximum Transmission Unit.

The maximum packet size that can be transmitted.

NC-SI

Network Controller Sideband Interface.

An electrical interface and protocol for out-of-band system management.

NIC

Network Interface Controller.

NUMA

Non-Uniform Memory Access.

A multiprocessing design where memory is local to clusters of processors.

Onload

A high performance user-level network stack from AMD, which accelerates TCP and UDP network I/O.

PCIe

Peripheral Component Interconnect Express.

A high-speed serial bus used to connect components.

PF

Physical Function.

A PCIe physical device.

RS-FEC

A type of Forward Error Correction also known as Reed Solomon.

RSS

Receive Side Scaling.

Enables packet receive-processing to scale with the number of available CPU cores.

RX, Rx

Receive.

SECDED

Single Error Correction / Double Error Detection.

Error processing that can correct a 1-bit error, and detect a 2-bit error.

SFP

Small Form-factor Pluggable.

A single-channel network transceiver design.

SMBus

System Management Bus.

A single-ended two-wire bus for lightweight communication between system components.

TSO

TCP Segmentation Offload.

Offloads the splitting of outgoing TCP data into packets to the adapter.

TX, Tx

Transmit.

UEFI

Unified Extensible Firmware Interface.

Provides support for disk-less booting to a target operating system.

UUID

Universally Unique Identifier.

A 128-bit identifier that is unique and persistent.

XCUX35

The FPGA used on an X3522.