When you plan pinouts for an SSI Technology Versal device, recognize that the bottom SLR (SLR0) contains the XPIO banks. The SLRs do not have them spread throughout, unlike in previous columnar architectures. In most cases, you must locate the logic associated with an XPIO external interface in the same SLR as the I/O and XPHY logic.
If you use the hardened DDR memory controller, the associated data movement can travel over the NoC. It can reach another SLR by leveraging the dedicated NoC routing without adding complexity to the PL design implementation. When deciding on the placement of an external interface, consider the following techniques:
- For smaller interfaces, group all pins within a single XPIO bank
- For larger interfaces, group all pins in multiple adjacent XPIO banks
- Place hardened DDR memory controllers in the corner banks that do not have PL access
- Balance CCIO or CMT components across XPIO banks
- For GT interfaces, group all GT pins within a minimal number of Quads
- For GT interfaces connected to another hard IP (for example, PCIe, MRMAC, or DCMAC), keep all GT pins within the same SLR. Place GT pins on the same side of the SLR as the hard IP. This means the left or right side. Ideally, position them in the same or adjacent clock region.
- For GT interfaces requiring access to MMCM or clock multiplexer resources, place the GT pins in the same SLR as the XPIO. This reduces clock routing utilization