Required Information for Pin Assignment - Required Information for Pin Assignment - 2026.1 English - UG1506

Versal Adaptive SoC Board System Design Methodology Guide (UG1506)

Document ID
UG1506
Release Date
2026-07-22
Version
2026.1 English

For the tools to work effectively, you must provide as much information about the I/O characteristics and topologies as possible. You must specify the electrical characteristics, including the I/O standard, drive, slew, and direction of the I/O.

You must also take into account all other relevant information, including connectivity, clock topology, and timing constraints. Clocking choices in particular can have a significant influence on pinout selection and vice versa.

For IP that have I/O requirements, such as transceivers, PCIe® cores, memory interfaces, and high-speed I/O interfaces, you must configure the IP before completing I/O pin assignment. Refer to this link in the Vivado Design Suite User Guide: I/O and Clock Planning (UG899). It provides more information on specifying the electrical characteristics for an I/O.

Important: Not all I/O can reach the programmable logic (PL) region in Versal devices, such as some I/O in the corner banks. For more information, refer to the following documents:
  • Versal Adaptive SoC Clocking Resources Architecture Manual (AM003)
  • Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)
  • Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013)