The AMD Vivado™ IDE allows you to interactively explore, visualize, assign, and validate the I/O ports and clock logic in your design. The environment ensures correct-by-construction I/O assignment. It also provides visualization of the external package pins in correlation with the internal die pads.
You can visualize the data flow through the device and properly plan I/Os from both an external and internal perspective. After you assign and configure the I/Os through the Vivado IDE, you automatically create constraints for the implementation tools.
AMD recommends I/O planning high-speed interfaces in the following order to achieve the maximum utilization of available XPHY logic resources:
- Integrated DDR memory controller via NoC
- Soft memory controllers
- Advanced IO Wizard/X5IO Wizard
- I/O logic
Similarly, AMD recommends planning all gigabit transceiver (GT) blocks usage at the same time in Vivado IP integrator. This enables optimally sharing GT Quads across several soft IP such as Aurora, Ethernet, JESD, and so on. Hard IP such as MRMAC, DCMAC, or PCIe do not share GT Quads.
For more information on I/O and clock planning capabilities, refer to the Vivado Design Suite User Guide: I/O and Clock Planning (UG899).