AMD recommends that you select clocking resources as one of the first steps of your design, well before pinout selection. Your clocking selections can dictate a particular pinout and can also direct logic placement for that logic. Proper clocking selections can yield superior results. Consider the following:
- Constraint creation, particularly in large devices with high utilization in conjunction with clock planning.
- Manual placement of clocking resources if needed for design closure.
- SelectIO™ interfaces using PHY Logic for high-performance I/O Interfaces, which exist at the bottom row of the device and have specific clocking requirements that are met by using the Advanced IO Wizard/X5IO Wizard and the Advanced I/O Planner.
- Corner banks that exist below processing system (PS) and gigabit transceiver (GT) resources have limited clocking capability, such as no direct access to BUFGCE_DIV and BUFGCTRL resources.
- Additional device-specific functionality that might require up-front planning to avoid issues and take advantage of device features. For information on Versal device features, see this link in the Versal Adaptive SoC Clocking Resources Architecture Manual (AM003), Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010), and the Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013).
Important: Only GC pins can
route to PLL/MMCM. Only XCC pins can be used for strobes (capture clock) for PHY
receive interfaces. The choice of the XCC determines how many and which PHY you can
reach with the strobe. See the
Versal
Adaptive SoC SelectIO Resources Architecture Manual (AM010) for further information on these rules.