Boot and Configuration - Boot and Configuration - 2025.2 English - UG1506

Versal Adaptive SoC Board System Design Methodology Guide (UG1506)

Document ID
UG1506
Release Date
2025-12-17
Version
2025.2 English

AMD Versalâ„¢ devices have a centralized platform management controller (PMC) responsible for the boot-up process, security, power management, and debug interfaces to the programmable logic (PL), such as JTAG and debug core connectivity. Some Versal devices include a separate power domain for the PMC, and in other Versal devices, the low-power domain includes the PMC. The PMC power domain must be powered and must perform boot-up prior to configuring the PL, NoC programming interface (NPI), and processing system (PS) elements. The Versal device PMC executes the BootROM and platform loader and manager (PLM) for booting.

Versal devices can boot through PMC multiplexed I/O (MIO) pins from an external, non-volatile memory device. Devices can also boot from an external smart source, such as a microprocessor or microcontroller.

When board planning, consider boot mode and peripheral mode usage up front to ensure the required options do not reside on conflicting MIO. For information about supported boot modes, MIO used, and trade-offs, see the Versal Adaptive SoC Technical Reference Manual (AM011) or Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026).