When designing a board, it is important to consider which interfaces and pins can assist with debug capability beyond configuration. For example, AMD recommends that you ensure the JTAG interface is accessible even when the interface is not the primary configuration mode. The JTAG interface allows you to check the device ID, check the device DNA information, and read key status registers for debug. You can also use the interface to enable indirect flash programming solutions during prototyping.
In addition, signals such as ERROR_OUT and DONE are critical for device configuration debug. AMD recommends that you connect the DONE signals to light-emitting diodes (LEDs) using LED drivers and pull-ups.
See the Primary Boot Interfaces Table in the technical reference manual for your targeted primary boot mode setting and JTAG boot mode setting. Connect the MODE[3:0] pins to VCCO_503 using a 4.7 kΩ (or stronger) resistor or to ground using a 1 kΩ (or stronger) resistor to achieve the targeted primary boot mode setting. Add switches or jumpers to allow the MODE[3:0] pins to be set to the alternate JTAG boot mode for board manufacturing JTAG tests, board bring-up, or device debug. For recommended JTAG interface access and pull-up values, see this link in the Versal Adaptive SoC PCB Design User Guide (UG863) and Versal Adaptive SoC Schematic Review Checklist (XTP546).
Some devices containing multiple super logic regions (SLRs) can have multiple instances of the dedicated PMC pins listed below. Where there are multiple instances of these pins, all instances of each pin set must be connected to the same source.
- MODE0
- MODE1
- MODE2
- MODE3
- POR_B
- PUDC_B
- REF_CLK
For the chosen boot mode, see the corresponding PMC boot interface PCB guidelines at this link in the Versal Adaptive SoC PCB Design User Guide (UG863).