System Validation Planning - System Validation Planning - 2026.1 English - UG1504

System validation planning for AMD Versal™ adaptive SoC requires that you build key infrastructure into the system, as defined in the previous chapters. Systematic validation of overall design features, performance, and power consumption enables qualification of a system as production worthy. This chapter covers key areas of focus when planning for system validation based on your system design type. For information on validation, refer to this link in the Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388).

Following are the typical steps when planning for system-level validation:

• Power-up and power supply check
• Basic boot and device configuration
• Bring-up of functional subsystems of the device
• Bring-up of software stack and any runtime drivers or application programming interfaces (APIs)
  Note: This step is optional for some systems.
• Performance validation
• Power validation

During power-up and supply validation, system designers must refer to the Versal Architecture and Product Data Sheet: Overview (DS950). The system designers must ensure all supplies are at the expected level and current consumption in various domains is as expected. The system designer must plan to conduct testing on the voltage domains on the boards based on the supply merging done in the system. The designer can obtain currents in different domains using either the PDM tool or report_power based on the estimates for the design.

After the power supply and current consumption looks healthy, the next bring-up phase is usually device configuration. A typical method for initial device bring-up is to use the JTAG port on the Versal device. The device can be detected and addressed from the standard AMD Vivado™ Hardware Manager, as described in the Vivado Design Suite User Guide: Programming and Debugging (UG908). In addition, Versal adaptive SoC has a sophisticated System Monitor that allows monitoring of the on-chip supplies and temperature. The hardware designer can follow the requirements in the Versal Adaptive SoC System Monitor Architecture Manual (AM006) to enable the use of the System Monitor.

After initial bring-up, the focus in hardware-only systems is to bring up the internal hardened IP subsystems. This includes any complex GT and I/O as well as DDR memory controller subsystems in the design. For more information, see the hardware validation sections in the following resources:

• For NoC/DDR memory bring-up on silicon, refer to the following documents:
  • Vivado Design Tutorials: Versal Network on Chip/Multiple DDR Memory Controllers
  • This link in the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)
  • Programmable Network on Chip (NoC2) LogiCORE IP Product Guide (PG406)
  • Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456)
• For initial bring-up of the AI Engine subsystem, refer to the Beamforming in the Vitis Tutorials: AI Engine.
• For the PS subsystem, refer to the Versal Adaptive SoC Embedded Design Tutorial.

Basic tests establish the health of the overall Versal adaptive SoC subsystems. The system designer can then start the bring up of the actual functional model of the system. This typically involves some test development at a system level driven by the functionality of the overall system design. The test development can involve a software stack, depending on the type of system.

The system designer establishes the basic functionality of the system design. Then, the system designer runs performance-level test cases. These test cases calibrate and validate the key performance requirements. The following are examples:

• Signal processing throughput of a 64-antenna system, as shown in the Beamforming in the Vitis Tutorials: AI Engine.
• Images per second for image recognition in the Modified National Institute of Standards and Technology (MNIST) database. This uses the LeNet convolutional neural network (CNN). Refer to the Vitis Tutorials: AI Engine.
• For hardware-only systems, NoC/DDR performance, as shown in the Vivado Design Tutorials: Versal Network on Chip/DDR Memory Controller Performance Tuning.

With the design running at performance, the system designer can make power measurements for both static and dynamic power on the Versal device. To plan for power measurements, the system designer must ensure that the board design allows access to the power management integrated circuit (PMIC) interfaces. The PMIC interfaces enable live current measurements on the system running at performance.

The following table summarizes system validation based on your design type.