The AMD Versal™ adaptive SoC includes a debug architecture that enables enhanced system debug methodology capabilities. This debug architecture operates in any environment, including the lab, data center, and edge computing environments. For more information on debugging, refer to this link in the Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388).
The Versal adaptive SoC debug architecture consists of a centralized debug packet controller (DPC), which is the packet processing engine of the debug architecture. The DPC processes the packets and refers to them as the debug and trace packets (DTP). The DPC decodes these packets to determine the commands, the destinations, and any potential higher-level flow control and management tasks. The DPC processes the DTP sent by a host and executes any commands embedded in the packets. After processing, it generates responses and sends them back to the host.
For more information on the DPC, refer to the following documents:
- This link in the Versal Adaptive SoC Technical Reference Manual (AM011)
- This link in the Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)
- Versal Adaptive SoC Security Manual (UG1508)
- Versal AI Edge Series Gen 2 and Prime Series Gen 2 Security Manual (UG1724)