Debug the programmable logic (PL) and hard blocks if you encounter situations that are difficult to replicate in PL logic simulation. The PL and hard blocks support logic debug using the following ChipScope™ debug IP cores and hard blocks:
- AXI Streaming Integrated Logic Analyzer (AXIS-ILA)
- The AXIS-ILA core allows you to perform in-system debugging of post-implemented designs. It triggers on-hardware events and captures data at design speeds.
- AXI Streaming Virtual Input/Output (AXIS-VIO)
- The AXIS-VIO core allows you to monitor and drive design signals in real time. This core replaces physical input or output elements such as switches or light-emitting diodes (LEDs).
- Integrated Bit Error Ratio Tester (IBERT) GTY/GTYP/GTM
- The Versal adaptive SoC GTY/GTYP/GTM contains built-in IBERT Serial Analyzer functionality. This functionality allows in-system serial I/O validation and debug. This solution requires no additional PL IP.
- NoC DDR Memory Controller Calibration Debug
- The DDR memory controller integrated into the Versal adaptive SoC NoC supports a calibration debug interface accessible through the AMD Vivado™ Hardware Manager.
- PCI Express Link Debug
- The Versal adaptive SoC PCI Express® Integrated Block supports a link debug interface. If enabled, you can view the Link Training and Status State Machine (LTSSM) state transitions in the Vivado Hardware Manager.