Performance Modeling in Vivado IP Integrator - Performance Modeling in Vivado IP Integrator - 2026.1 English

Performance Modeling in Vivado IP Integrator - Performance Modeling in Vivado IP Integrator - 2026.1 English - UG1504

Versal Adaptive SoC System and Solution Planning Methodology Guide (UG1504)

Document ID

UG1504

Release Date

2026-07-22

Version

2026.1 English

The two stages can decompose performance modeling in Vivado IP integrator:

NoC/DDR memory interface dataflow modeling
Accelerator block dataflow modeling

In the first stage, you model the NoC dataflow using AMD traffic generator IP. You can configure it to generate transactions that resemble accelerator dataflow. For example, the accelerator requires a three-dimensional data cube to be processed. The data is arranged in a linear format in DDR memory, but the fetch address from the NoC master is not linear. You can configure the traffic generators for the required addressing mode (for example, three-dimensional) and monitor performance in the NoC-PL interface.

If DRAM efficiency usually causes lower-than-expected throughput, tune the DRAM address map to enhance the DRAM interface efficiency. In addition, the NoC provides quality of service (QoS) options. Depending on the traffic class, you can tune the QoS values for each NoC master and slave to meet application needs. For example, you can configure video applications that require the lowest level of latency for low latency traffic. Configure other NoC masters for best effort traffic.

In the next stage, you model the accelerator block by generating traffic for the accelerator that mimics actual dataflow from the NoC/DDR memory. If the accelerator interface supports the AXI4 streaming protocol (for example, AI Engine blocks), you can use AMD traffic generators or simulation PLIOs. Use them to model the traffic and tune the performance. You can tune the NoC and accelerator configuration based on the performance reported by monitor blocks.

Recommended: Performing traffic modeling separately for the NoC/DDR memory and the accelerator hardware helps with parallel evaluation of each block. This allows you to tune configurations and parameters before deploying the solution into a larger system where simulation time is often a bottleneck.

For more information, refer to the following documents:

This link in the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)
This link in the Programmable Network on Chip (NoC2) LogiCORE IP Product Guide (PG406)
Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456)
NoC DDR Memory Controller Versal Device Architecture Tutorials available from the GitHub repository