The main objective of this step is to reduce risk and identify gaps in assumptions made earlier. With the strawman proposal planned, it is important to verify that the proposal solves the problem.
For algorithms mapped to AI Engine, you can inspect the Vitis Libraries to see if an existing library block element matches your needs. If so, run quick simulations to understand throughput and latency performance of those library blocks.
Otherwise, it is useful to develop and investigate candidate vectorization options and consider how to use the SIMD processor to improve throughput. This can involve coding up kernels in isolation to identify the number of cycles required to loop through some data.
Algorithm Vectorization for AI Engine:
- Optimize data flow for efficient lane vectorization
- Early AI Engine API or intrinsic selection for key kernels
- Analysis of vector register requirements and utilization
- Visualize and plan lane assignments using Excel spreadsheets
Rapid Prototyping of AI Engine subsystems:
- Resource estimation including tile count, buffer usage, PLIO resources, stream array traffic, and so on.
- Assess latency feasibility with early data flow simulations
- Assess throughput feasibility via prototype kernel coding, Initiation Interval (II) loop analysis, and so on.
Similarly, for algorithms mapped to PL, this process applies when the algorithm targeted on an earlier device or technology node. It involves re-synthesizing the code on newer technology to get early estimates on PL resources needed (BRAM, LUTs, DSPs, FF, and so on). It also assesses FMAX feasibility. Alternatively, Vitis HLS enables rapid prototyping of newer functionality.
You can implement and profile functionality mapped to the processor to understand performance.
Use the Power Design Manager (PDM) to perform Early Power Analysis for AI Engine, PL, embedded blocks, interfaces, and other components. For more information, refer to the Power Design Manager User Guide (UG1556).
Designs using packet switching can have interface bandwidth between the blocks change depending on what is occurring in the system. For such designs, traffic generator analysis needs to be performed. You can abstract the compute aspect of the system here. You can also generate random source packets and inspect any possible bandwidth bottlenecks. For more information, refer to this link in the AI Engine Tools and Flows User Guide (UG1076).