Data-intensive applications demand high-bandwidth memory. The best approach is to construct an application-specific memory hierarchy. This includes memory caching from DDR memory to PL RAMs, such as UltraRAM/BRAM.
Versal devices can access the DDR memory through the NoC. The device fabric connects to the DDR memory. The NoC connects the Arm Cortex-A72 and the AI Engines. Using DMA data movers in the PL, you can coordinate data movement to and from the hard IP to the DDR memory. You can leverage intermediate PL RAM stages for caching or data buffering.
Versal devices provide access to DDR memory using DMAs. The hard memory controller and NoC connect the DDR memory to the device fabric and other hard IP. You can use DMA data movers in the PL to coordinate data movement to and from the DDR memory. You can also configure the NoC for maximum bandwidth using the DDR memory controllers available on the Versal device.