Iterate to System Feasibility - Iterate to System Feasibility - 2026.1 English - UG1504

Versal Adaptive SoC System and Solution Planning Methodology Guide (UG1504)

Document ID
UG1504
Release Date
2026-07-22
Version
2026.1 English

After completing early prototyping, you discover that there is a challenge meeting one of the earlier assumptions. This means that you need to iterate on the Solution Synthesis step to create a modified strawman, then proceed with the rest of the steps.

After completing these steps, you can define the following with minimal risk.

Device Selection and Speed Grade:

  • Identify a couple of device options that can meet or slightly exceed the resource profile of the strawman solution. Provision for some additional resources to include future enhancements.
  • Identify a couple of footprint-compatible packaging options. These options must provide enough flexibility to achieve additional resources and avoid board-level re-spin if you need a larger device.

Initial Definition of custom platform defines:

  • I/O ring and devices interfaces
  • AI Engine/PL interface definition (using the interface tiles)
  • NoC architecture
  • Design work can proceed to begin constructing the custom platform

Data flow template model of AI Engine array provides:

  • Early mapper/router validation
  • Initial buffer placement and location constraints
  • Confirmation of throughput vs. data flow plan