Iterate to System Feasibility - 2024.1 English

Versal Adaptive SoC System and Solution Planning Methodology Guide (UG1504)

Document ID
UG1504
Release Date
2024-06-19
Version
2024.1 English

After prototyping the risky computations, it was discovered that the achieved throughput for the 32-tile solution is 24.2 Mpps compared to what it was predicated 39 Mpps. Using the characterization data produced in the earlier step, you can predict how throughput will change as you scale up the design.

Figure 1. Hough Transform Projections

The total number of tiles needed to achieve 220 Mpps is ~275 tiles. Review the Versal AI Core Series Product Selection Guide (XMP452) and the VC1902 with -2M is a good choice because it contains the necessary number of tiles plus additional margin. The -2M speed grade gives a 1.25 GHz AI Engine clock, as described in this link in the Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957).