Hardware-Only System Validation Planning - Hardware-Only System Validation Planning - 2026.1 English - UG1504

Versal Adaptive SoC System and Solution Planning Methodology Guide (UG1504)

Document ID
UG1504
Release Date
2026-07-22
Version
2026.1 English

Hardware-only system designs typically include a processor core, hardened IP, and programmable logic (PL). You can use the following system-level debugging tools to diagnose the system-level issues in your design:

  • Xilinx System Debugger (XSDB)
  • AXI Streaming Integrated Logic Analyzer (AXIS-ILA)
  • AXI Streaming Virtual Input/Output (AXIS-VIO)
  • Integrated Bit Error Ratio Tester (IBERT)

The first step in system-level design debugging is to read the hardware status using XSDB tool. Then, use the tools listed in the following table to find the root cause of the issues.

Note: For information on XSDB commands, refer to the Software Debugger Reference Guide (UG1725).
Table 1. Hardware-only System Debug Tools
Hardware Debug Tool
Processor-based system-level debug
  • XSDB
PL logic system debug
  • AXIS-ILA
  • AXIS-VIO
PL logic debug
  • IBERT
  • AXIS-ILA
  • AXIS-VIO
Hardened IP
  • IBERT
  • AXIS-ILA
  • AXIS-VIO
GT I/O hard block debug
  • IBERT