The integrated Aurora 64B/66B block in the PS accesses the DPC through a high-speed GT-based interface. High-Speed Debug Port (HSDP) is the protocol to access DPC. HSDP provides bidirectional access to the device from an external host debug/trace module, allowing for high-speed debug and trace operations. You can connect the SmartLynq+ module to the Aurora interface to access the HSDP in the Versal adaptive SoC.
For more information, refer to this link in the SmartLynq+ Module User Guide (UG1514). For information on HSDP quad availability, refer to the following documents:
- This link in the Versal Adaptive SoC Technical Reference Manual (AM011)
- Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)
Note: The integrated HSDP Aurora interface is not
available in all Versal adaptive SoCs. This interface
requires additional configuration in the Control, Interfaces, and Processing (CIPS) IP
and the use of additional Gigabit Transceivers.