The primary challenge to resolve as part of system design architecture is power and performance optimization. Your choice of acceleration hardware, whether PL or AI Engines, depends on the type of algorithm and data ingress and egress paths. This applies to streaming data ingress and egress to and from sensors, for example LiDAR, RADAR, and dual-camera vision systems.
In this case, data is available to fabric through high-speed transceivers. External protocol interfaces on AXI4-Stream buses aggregate this data. Distribute the data to the PL or AI Engines.
The processor subsystem (PS), programmable logic (PL), and AI Engines form a tightly-integrated, heterogeneous compute platform. PS provides complex software support. PL provides flexible custom compute and data movement. Given their high compute density, AI Engines are well suited for vector-based algorithms.
During this step, you develop a mapping of the core application and of each algorithm to the most appropriate architectural area. For example, AI Engine, PS, PL, NoC, and DDR memory controller in the Versal adaptive SoC. This consists of mapping all of the major blocks in the application and considering requirements on these major blocks in terms of bandwidth and availability. This application mapping and design partition step is manual.
You can implement additional features, such as clock gating, for PL and AI Engine regions you do not use concurrently. Use the same approach as FPGA architectures to handle traditional multi-clock domain fabric design and datapath clock domain crossing.