This guide includes high-level information, design guidelines, and design decision trade-offs for the following topics:
- System Design Types
- Provides an overview of the different system design types and design flows supported for each Versal device series.
- System Design Planning Methodology Flow
- Describes the recommended methodology when planning your system design, including special considerations based on your system design type.
- AI Engine System Partitioning Planning
- Provides information on how to partition a hetrerogenous Versal adaptive SoC system by balancing compute, storage, and bandwidth, using an iterative methodology that minimizes risk and identifies a feasible architecture early.
- Power and Thermal Planning
- Covers system design considerations related to power estimation, thermal design, power delivery, and decoupling.
- System Debug Planning
- Provides information on the Versal adaptive SoC debug interfaces as well as high-level information on debugging the AI Engine and processing system (PS).
- System Verification Planning
- Provides high-level simulation recommendations for Versal adaptive SoC.
- System Validation Planning
- Provides information on key areas of focus when planning for system validation based on your system design type.
Also, this guide covers the architecture and design flow for the following device series:
- Versal Prime Series Gen 2
- Versal Prime Series
- Versal Premium Series
- Versal HBM Series
- Versal AI Core Series
- Versal AI Edge Series Gen 2
- Versal AI Edge Series
Both architectures are similar. This guide provides IP/block and design flow examples based on the IP/blocks in the Versal AI Core Series VC1902. The example design flow is generally applicable to all Versal devices with minor variations. For IP/blocks available in the devices of each series, refer to the Versal Architecture and Product Data Sheet: Overview (DS950).
The following table shows the differences between architectures.
| Versal Prime, Premium, HBM, AI Core, and AI Edge Series Docs/Terms | Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 Docs/Terms | |
|---|---|---|
| Series |
|
|
| PS – Application Processors | Versal Adaptive SoC Technical Reference Manual (AM011) ( Arm® Cortex®-A72) | Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026) (Arm Cortex-A78AE) |
| PS – Real-time Processors | Versal Adaptive SoC Technical Reference Manual (AM011) (Arm Cortex-R5F) | Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026) (Arm Cortex-R52) |
| PS – Traditional Design Flow Configuration Wizards | Control, Interface and Processing System LogiCORE IP Product Guide (PG352) 1 | Processing System Wizard LogiCORE IP Product Guide (PG450) |
| AI Engine | Versal Adaptive SoC AIE-ML v2 Architecture Manual (AM027) (AIE-ML v2) | |
| NoC/DDRMC | Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313) (DDR4 and LPDDR4/4X) | Programmable Network on Chip (NoC2) LogiCORE IP Product Guide (PG406) and Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456) (DDR5 and LPDDR5/5X) |
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