XPM_NSU_STRM - 2025.1 English - Parameterized Macro: AXI Streaming (AXI Full) NOC Slave Unit - UG1485

Versal Architecture Premium Series Libraries Guide (UG1485)
Document ID
UG1485
Release Date
2025-09-17
Version
2025.1 English

Parameterized Macro: AXI Streaming (AXI Full) NOC Slave Unit

  • MACRO_GROUP: XPM
  • MACRO_SUBGROUP: NOC

Introduction

This macro is used to instantiate AXI Streaming (AXI Full) NOC Slave Unit.

Port Descriptions

Port Direction Width Domain Sense Handling if Unused Function
m_axis_aclk Input 1 NA EDGE_RISING Active Master Interface Clock: All signals on slave interface are sampled on the rising edge of this clock.
m_axis_tdata Output DATA_WIDTH m_axis_aclk NA Active TDATA: The primary payload that is used to provide the data that is passing across the interface. The width of the data payload is an integer number of bytes.
m_axis_tdest Output DST_ID_WIDTH m_axis_aclk NA Active TDEST: Provides routing information for the data stream.
m_axis_tid Output ID_WIDTH m_axis_aclk NA Active TID: Identification tag for the data transfer
m_axis_tkeep Output DATA_WIDTH / 8 m_axis_aclk NA Active TKEEP: is the byte qualifier that indicates whether content of the associated byte of TDATA is processed as part of the data stream.
m_axis_tlast Output 1 m_axis_aclk LEVEL_HIGH Active TLAST: Indicates the boundary of a packet.
m_axis_tready Input 1 m_axis_aclk LEVEL_HIGH Active TREADY: Indicates that the receiver can accept a transfer in the current cycle.
m_axis_tvalid Output 1 m_axis_aclk LEVEL_HIGH Active TVALID: indicates the Transmitter is driving a valid transfer. A transfer takes place when both TVALID and TREADY are asserted.

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog No

Available Attributes

Attribute Type Allowed Values Default Description
DATA_WIDTH DECIMAL 512, 128, 256 512 Defines the width of the DATA ports, s_axi_rdata, s_axi_wdata.
DST_ID_WIDTH DECIMAL 0 to 4 4 Defines the width of the TDEST port
ID_WIDTH DECIMAL 0 to 6 6 Defines the width of the ID ports, TID
NOC_FABRIC STRING "VNOC", "BLI", "pl", "pl_hbm" "VNOC"
  • "VNOC"/"pl" - Choosing the VNOC NMU of given device
  • "BLI"/"pl_hbm" - Disables Packet FIFO mode

VHDL Instantiation Template


-- xpm_nsu_strm: AXI Streaming (AXI Full) NOC Slave Unit
-- Xilinx Parameterized Macro, version 2025.1

xpm_nsu_strm_inst : xpm_nsu_strm
generic map (
   DATA_WIDTH => 512,    -- DECIMAL
   DST_ID_WIDTH => 4,    -- DECIMAL
   ID_WIDTH => 6,        -- DECIMAL
   NOC_FABRIC => "VNOC"  -- STRING
)
port map (
   m_axis_tdata => m_axis_tdata,   -- DATA_WIDTH-bit output: TDATA: The primary payload that is used to provide the data that is passing across
                                   -- the interface. The width of the data payload is an integer number of bytes.

   m_axis_tdest => m_axis_tdest,   -- DST_ID_WIDTH-bit output: TDEST: Provides routing information for the data stream.
   m_axis_tid => m_axis_tid,       -- ID_WIDTH-bit output: TID: Identification tag for the data transfer
   m_axis_tkeep => m_axis_tkeep,   -- DATA_WIDTH/8-bit output: TKEEP: is the byte qualifier that indicates whether content of the associated byte
                                   -- of TDATA is processed as part of the data stream.

   m_axis_tlast => m_axis_tlast,   -- 1-bit output: TLAST: Indicates the boundary of a packet.
   m_axis_tvalid => m_axis_tvalid, -- 1-bit output: TVALID: indicates the Transmitter is driving a valid transfer. A transfer takes place when
                                   -- both TVALID and TREADY are asserted.

   m_axis_aclk => m_axis_aclk,     -- 1-bit input: Master Interface Clock: All signals on slave interface are sampled on the rising edge of this
                                   -- clock.

   m_axis_tready => m_axis_tready  -- 1-bit input: TREADY: Indicates that the receiver can accept a transfer in the current cycle.
);

-- End of xpm_nsu_strm_inst instantiation

Verilog Instantiation Template


// xpm_nsu_strm: AXI Streaming (AXI Full) NOC Slave Unit
// Xilinx Parameterized Macro, version 2025.1

xpm_nsu_strm #(
   .DATA_WIDTH(512),    // DECIMAL
   .DST_ID_WIDTH(4),    // DECIMAL
   .ID_WIDTH(6),        // DECIMAL
   .NOC_FABRIC("VNOC")  // STRING
)
xpm_nsu_strm_inst (
   .m_axis_tdata(m_axis_tdata),   // DATA_WIDTH-bit output: TDATA: The primary payload that is used to provide the data that is passing across the
                                  // interface. The width of the data payload is an integer number of bytes.

   .m_axis_tdest(m_axis_tdest),   // DST_ID_WIDTH-bit output: TDEST: Provides routing information for the data stream.
   .m_axis_tid(m_axis_tid),       // ID_WIDTH-bit output: TID: Identification tag for the data transfer
   .m_axis_tkeep(m_axis_tkeep),   // DATA_WIDTH/8-bit output: TKEEP: is the byte qualifier that indicates whether content of the associated byte
                                  // of TDATA is processed as part of the data stream.

   .m_axis_tlast(m_axis_tlast),   // 1-bit output: TLAST: Indicates the boundary of a packet.
   .m_axis_tvalid(m_axis_tvalid), // 1-bit output: TVALID: indicates the Transmitter is driving a valid transfer. A transfer takes place when both
                                  // TVALID and TREADY are asserted.

   .m_axis_aclk(m_axis_aclk),     // 1-bit input: Master Interface Clock: All signals on slave interface are sampled on the rising edge of this
                                  // clock.

   .m_axis_tready(m_axis_tready)  // 1-bit input: TREADY: Indicates that the receiver can accept a transfer in the current cycle.
);

// End of xpm_nsu_strm_inst instantiation